The present invention generally relates to a method for forming semiconductor packages and devices formed and more particularly, relates to a single-step method for forming semiconductor packages in which a bumping and a bonding step are carried out simultaneously and the packages formed.
In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques in such high density devices. Conventionally, a flip-chip attachment method has been used in packaging of semiconductor chips. In the flip-chip attachment method, instead of attaching a semiconductor die to a lead frame in a package, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out in an evaporation method by using a composite material of tin and lead through a mask for producing a desired pattern of solder bumps. The technique of electrodeposition has been more recently developed to produce solder bumps in flip-chip packaging process.
Other techniques that are capable of solder-bumping a variety of substrates to form solder balls have also been proposed. The techniques generally work well in bumping semiconductor substrates that contain solder structures over a minimal size. For instance, one of such widely used techniques is a solder paste screening method which has been used to cover the entire area of an eight inch wafer. However, with recent trend in the miniaturization of device dimensions and the necessary reduction in bump-to-bump spacing (or pitch), the use of the solder paste screening technique has become more difficult.
Other techniques for forming solder bumps such as the controlled collapse chip connection (C4) technique and the thin film electrodeposition technique have also been used in recent years in the semiconductor fabrication industry. The C4 technique is generally limited by the resolution achievable by a molybdenum mask which is necessary for the process. Fine-pitched solder bumps are therefore difficult to be fabricated by the C4 technique. Similarly, the thin film electrodeposition technique which also requires a ball limiting metallurgy layer to be deposited and defined by an etching process which has the same limitations as the C4 technique. For instance, a conventional thin film electrodeposition process for depositing solder bumps is shown in FIGS. 1Axcx9c1F.
A conventional semiconductor structure 10 is shown in FIG. 1A. The semiconductor structure 10 is built on a silicon substrate 12 with active devices built therein. A bond pad 14 is formed on a top surface 16 of the substrate 12 for making electrical connections to the outside circuits. The bond pad 14 is normally formed of a conductive metal such as aluminum. The bond pad 14 is passivated by a final passivation layer 20 with a window 22 opened by a photolithography process to allow electrical connection to be made to the bond pad 14. The passivation layer 20 may be formed of any one of various insulating materials such as oxide, nitride or organic materials. The passivation layer 20 is applied on top of the semiconductor device 10 to provide both planarization and physical protection of the circuits formed on the device 10.
Onto the top surface 24 of the passivation layer 20 and the exposed top surface 18 of the bond pad 14, is then deposited an under bump metallurgy layer 26. This is shown in FIG. 1B. The under bump metallurgy (UBM) layer 26 normally consists of an adhesion/diffusion barrier layer 30 and a wetting layer 28. The adhesion/diffusion barrier layer 30 may be formed of Ti, TiN or other metal such as Cr. The wetting layer 28 is normally formed of a Cu layer or a Ni layer. The UBM layer 26 improves bonding between a solder ball to be formed and the top surface 18 of the bond pad 14.
In the next step of the process, as shown in FIG. 1C, a photoresist layer 34 is deposited on top of the UBM layer 26 and then patterned to define a window opening 38 for the solder ball to be subsequently formed. In the following electrodeposition process, a solder ball 40 is electrodeposited into the window opening 38 forming a structure protruded from the top surface 42 of the photoresist layer 34. The use of the photoresist layer 34 must be carefully controlled such that its thickness is in the range between about 30 xcexcm and about 40 xcexcm, preferably at a thickness of about 35 xcexcm. The reason for the tight control on the thickness of the photoresist layer 34 is that, for achieving a fine-pitched solder bump formation, a photoresist layer of a reasonably small thickness must be used such that a high imaging resolution can be achieved. It is known that, during a photolithography process, the thicker the photoresist layer, the poorer is the imaging process. To maintain a reasonable accuracy in the imaging process on the photoresist layer 34, a reasonably thin photoresist layer 34 must be used which results in a mushroom configuration of the solder bump 40 deposited therein. The mushroom configuration of the solder bump 40 contributes greatly to the inability of a conventional process in producing fine-pitched solder bumps.
Referring now to FIG. 1E, wherein the conventional semiconductor structure 10 is shown with the photoresist layer 34 removed in a wet stripping process. The mushroom-shaped solder bump 40 remains while the under bump metallurgy layer 26 is also intact. In the next step of the process, as shown in FIG. 1F, the UBM layer 26 is etched away by using the solder bump 40 as a mask in an wet etching process. The solder bump 40 is then heated in a reflow process to form solder ball 44. The reflow process is conducted at a temperature that is at least the reflow temperature of the solder material.
In recent years, chip scale packages (CSP) have been developed as a new low cost packaging technique for high volume production of IC chips. One of such chip scale packaging techniques has been developed by the Tessera Company for making a so-called micro-BGA package. The micro-BGA package can be utilized in an environment where several of the packages are arranged in close proximity on a circuit board or a substrate much like the arrangement of individual tiles. Major benefits achieved by a micro-BGA package are the combined advantages of a flip chip assembly and a surface mount package. The chip scale packages can be formed in a physical size comparable to that of an IC chip even though, unlike a conventional IC chip such as a flip chip, the chip scale package does not require a special bonding process for forming solder balls. Furthermore, a chip scale package may provide larger number of input/output terminals than that possible from a conventional quad flat package, even though a typical quad flat package is better protected mechanically from the environment.
A unique feature of the chip scale package is the use of an interposer layer that is formed of a flexible, compliant material. The interposer layer provides the capability of absorbing mechanical stresses during the package forming steps and furthermore, allows thermal expansion mismatch between the die and the substrate. The interposer layer, therefore, acts both as a stress buffer and as a thermal expansion buffer. Another unique feature of the chip scale package, i.e. such as a micro-BGA package, is its ability to be assembled to a circuit board by using conventional surface mount technology (SMT) processes.
In a typical micro-BGA package, a flexible interposer layer (which may contain circuit) is used to interconnect bond pads on an IC chip to an array of solder bump connections located on a flexible circuit. The flexible circuit, normally of a thickness of approximately 25 xcexcm, is formed of a polymeric material such as polyimide which is laminated to a silicon elastomer layer of approximately 150 xcexcm thick. The silicon elastomeric layer provides flexibility and compliance in all three directions for relief of stresses and thermal expansion mismatches. To further reduce the fabrication cost of IC devices, it is desirable that if a whole wafer can be passivated to seal the IC dies on the wafer, and then be severed into individual IC dies from the wafer such that not only the benefits of a chip scale package can be realized, the packaging cost for the IC dies may further be reduced.
A large number of IC chips are designed with a peripheral array of I/O pads. For modern high density devices, the pitch allowed between I/O pads is steadily decreasing. An I/O pad redistribution process is frequently necessary for changing a peripheral array to an area array in order to improve pitch between the conductive pads. During the redistribution process, metal traces are frequently used to extend bond pads from a peripheral area to a center area on the chip. Due to the limited space available for the metal traces, especially those traces that run an extended distance, it is desirable to produce metal traces that are stress buffered in order to assure the reliability of a chip.
The conventional flip chip bonding process requires multiple preparation steps for IC chips, i.e. the formation of aluminum bond pads on the chip, the under-bump-metallurgy process on the bond pads and the deposition of solder required in the bumping process. The substrate that the IC chip is bonded to requires a flux coating in order to ensure an acceptable bond strength is formed between the solder bumps and the conductive elements on the substrate surface. The flip chip bonding process further requires a reflow process for the bumps, a flux cleaning process to eliminate excess flux material from the surface of the bump, a drying process after the cleaning process, an underfill process for dispensing an underfill material, and an underfill curing process to minimize thermal stresses in the underfill and in the joint formed.
The conventional method for depositing solder bumps described above therefore presents a number of processing difficulties. For instance, one of the difficulties is the large volume of solder used to form a mushroom-shaped bump which impedes the process of making fine-pitched bumps. Another difficulty is the requirement of a flux coating step to ensure adhesion between a bump pad and a solder bump. The requirement of a solder reflow process further complicates the flip chip bonding method and increases its costs. It is therefore desirable to implement a flip chip bonding process that does not require separate processing bonding the bumps to a substrate.
It is therefore an object of the present invention to provide a single-step bumping/bonding method for forming semiconductor packages that does not have the drawbacks or shortcomings of the conventional method.
It is another object of the present invention to provide a single-step bumping/bonding method for forming semiconductor packages in which the formation of solder bumps and the bonding of an IC device to a substrate are carried out simultaneously.
It is a further object of the present invention to provide a single-step bumping/bonding method for forming semiconductor packages that does not require an underfill process.
It is another further object of the present invention to provide a single-step bumping/bonding method for forming semiconductor packages that is superior to either a wire bonding or a flip chip bonding method.
It is still another object of the present invention to provide a single-step bumping/bonding method for forming semiconductor packages capable of producing IC circuits utilizing area array input-output pads.
It is yet another object of the present invention to provide a single-step bumping/bonding method that is applicable to 3-D packaging, ultra-thin packaging and direct chip attachment techniques.
It is still another further object of the present invention to provide a semiconductor package of two electronic substrates electrically connected together by solder bumps which can be formed in a single bumping/bonding step.
It is yet another further object of the present invention to provide a semiconductor package of an IC chip/PCB board having electrical communication established therein between by solder balls formed in a single bumping/bonding step.
In accordance with the present invention, a semiconductor package of two electronic substrates electrically connected together by solder bumps and a single-step bumping/bonding method for forming such semiconductor packages are disclosed.
In a preferred embodiment, a semiconductor package of two electronic substrates that are electrically connected together by solder bumps can be provided which includes a first electronic substrate that has a first plurality of conductive pads formed on a first surface insulated from one another by a first insulating material layer, the first electronic substrate may further include a first plurality of apertures through the substrate, the first plurality of conductive pads and the first insulating material layer with one aperture corresponds to each conductive pad, a second electronic substrate that has a second plurality of conductive pads formed on a second surface insulated from one another by a second insulating material layer, the first plurality may be equal to or different from the second plurality, one of the first and second electronic substrates is a silicon wafer while the other one is a printed circuit board, a first plurality of solder bumps mechanically and electrically connecting the first plurality of conductive pads to the second plurality of conductive pads, and a first plurality of conductive plugs each filling one of the first plurality of apertures in electrical communication and formed integrally with one of the first plurality of solder bumps.
In the semiconductor package formed of two electronic substrates electrically connected together by solder bumps, the first electronic substrate may be a silicon wafer and the second electronic substrate may be a printed circuit board, or vice versa. The first electronic substrate may be a silicon wafer and the first plurality of conductive pads may further include a layer of under-bump-metallurgy (UBM) material on top. The first and the second plurality of conductive pads may be input/output (I/O) pads. The first electronic substrate may be a silicon wafer and the first insulating material layer may be a passivation layer. The second electronic substrate may be a printed circuit board and the second insulating material layer may be a solder mask. The first plurality of apertures each may have a sidewall coated with an adhesion promoter. The first plurality of solder bumps may be reflown into a plurality of solder balls. The first plurality of solder bumps may each have a height between about 50 xcexcm and about 100 xcexcm.
The present invention is further directed to a single-step bumping/bonding method for forming semiconductor packages which can be carried out by the operating steps of first providing a first electronic substrate that has a first plurality of conductive pads formed on a first surface insulated from one another by a first insulating material layer, forming a first plurality of apertures through the first electronic substrate, the first plurality of conductive pads and the first insulating material layer with one aperture corresponds to each conductive pad, providing a second electronic substrate that has a second plurality of conductive pads formed on a second surface insulated from one another by a second insulating material layer, the first plurality may be equal to or different than the second plurality, to one of the first and the second electronic substrate is a silicon wafer while the other is a printed circuit board, positioning the first electronic substrate juxtaposed to the second electronic substrate such that the first plurality of conductive pads faces the second plurality of conductive pads, and then depositing into the first plurality of apertures a solder material filling the apertures and forming a first plurality of solder bumps in-between the first and second electronic substrates mechanically and electrically connecting the first plurality of conductive pads to the second plurality of conductive pads.
The single-step bumping/bonding method for forming semiconductor packages may further include the step of providing the first electronic substrate in a silicon wafer and providing the second electronic substrate in a PCB. The method may further include the step of forming the first plurality of apertures by laser drilling or by micro-electro-mechanical system (MEMS) machining. The deposition step for the solder material may further include a solder injection or solder screen printing technique. The method may further include the step of heat treating the semiconductor package at a temperature higher than a reflow temperature of the solder material. The method may further include the step of annealing the first plurality of solder bumps to cause them reflown into solder balls. The method may further include the step of removing at least ⅓ of the total thickness of the first electronic substrate on an inactive side prior to the aperture-forming step. The method may further include the step of coating a sidewall in the first plurality of apertures with an adhesion promoter prior to depositing the solder material. It should be understood that the adhesion promoter not only enhances the adhesion of the solder material, but also improves the electrical properties such as eliminating current leakage. The method may further include the steps of depositing and patterning an under-bump-metallurgy layer onto the first plurality of conductive pads when the first electronic substrate is a silicon wafer prior to depositing the solder material. The method may further include a step of providing the first electronic substrate in a printed circuit board and the second electronic substrate in a silicon wafer.